OCR J277 · Component 01 · §1.1 · Paper 1

§1.1 Systems Architecture

What is the CPU, how does it execute instructions, and what makes one processor faster than another?

The CPU is the brain of any computer — it is where instructions are fetched, decoded, and executed. Every action your program takes passes through the fetch–execute cycle: the Control Unit fetches an instruction from the address stored in the Program Counter, decodes it, and either performs arithmetic in the ALU or moves data between registers. The four named registers in OCR's spec (MAR, MDR, PC, Accumulator) each have one job, and the exam tests whether students know exactly what each one holds: an address or a value.

Performance is controlled by three main levers. Clock speed sets how many cycles per second the CPU can complete — a faster clock means more instructions per second, but also more heat and power consumption. More cores allow multiple tasks to run in parallel, but only if the workload can be split. Cache is very fast memory sitting between the CPU and RAM; a larger cache means fewer slow round-trips to main memory. These levers interact and have diminishing returns — doubling clock speed will not double performance if the bottleneck is cache size.

Explain the role of the MAR and MDR in the fetch stage of the fetch–execute cycle. (4 marks) — Then: a student claims that "a CPU with more cores is always faster." Evaluate this claim.

Key terms

ALU (Arithmetic Logic Unit) — performs calculations and logical comparisons
CU (Control Unit) — directs the fetch–execute cycle; sends control signals
MAR (Memory Address Register) — holds the address to be read from/written to
MDR (Memory Data Register) — holds the data just fetched or about to be written
PC (Program Counter) — holds the address of the next instruction to fetch
Accumulator — holds intermediate results from ALU operations

What students must understand

Diagrams

Von Neumann architecture diagram: the CPU, containing registers, control unit and ALU, connected to main memory by the address, data and control buses
Von Neumann architecture. The CPU and main memory exchange addresses and data over buses, and instructions and data share the same memory.
Photograph of a desktop CPU package
The physical CPU, a desktop processor package.

Diagrams: PG Online (Paul Long), OCR J277 textbook. Used under the school site licence.

Linking questions

Practice

Video Support

Craig'n'Dave — OCR J277
1.1 Systems architecture — unit playlist